Peter Bendix

• Ph.D., Theoretical Physics, Univ. of British Columbia, Canada
• B.S., Physics, CalTech
• 25+ years industrial experience in engineering and management
• Device physics experience in MOS and bipolar modeling, circuit simulation, SPICE model
  parameter extraction, TCAD, E-Test, interconnect modeling and reliability physics

Leo G. Henry

• Ph.D., Material Science, UC Berkeley, USA
• 20+ years industrial experience in ESD testing methodology development and TLP testing
• A member of ESDA board of directors and its National Tutorial chair
• Board member of Silicon Valley EOS/ESD Society since 1994 (President 1996-1998)

Yoon J. Huh


• Ph.D., Electrical Engineering, Korea University, Korea
• 16+ years industrial experience in ESD protection, circuit design and process development
• In charge of ESD/LU reliability for all products at LSI Logic (1998-2004), currently ESD
consultant to LSI Logic
• Designed ESD protection scheme for standard/high speed I/O cells and cores, and published
  ESD/LU design rules for 0.35um-90nm node


Kyungjin (Jin) Min


• Ph.D., Electrical Engineering, North Carolina State University, USA
• 6+ years industrial experience in transistor design and process integration
• Developed 0.13um SOC (system on Chip) FE process, including logic, memory, mixed signal
and I/O devices

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