Consulting

What Can GTLeader Provide for ESD Design

More aggressive processes, rules and designs cause ESD failure mechanisms that were not observed previously.

I/O ESD protection by foundry and I/O library vendors usually over-protects I/O, and allows core circuit failure.

There is no one ESD protection scheme or device that can protect all circuit from ESD damage (no one-size-fits-all remedy !!).

• In-depth coverage on complete spectrum of chip making
- GTLeader’s expertise covers complete spectrum of chip making; processes, modeling,
  simulation, reliability, circuit design, packaging, etc.
- GTLeader’s ESD experts have fixed more than 300 designs from 0.5um to 0.13um
  technology node
- GTLeader has a whole chip level ESD protection solution as well as special and high speed
  I/O protection cells

• Design review
- GTLeader will review your design before tape-out to improve ESD performance
- GTLeader will provide ESD design rules and a super set of TSMC ESD design rules,
  covering core circuit protection schemes as well as I/O

• TLP Testing
- GTLeader provides TLP testing and analysis for FA and design verification