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Achievement and Works in Progress

GTLeader is developing.

• Transient latch-up testing (TLU)
• Accurate system level ESD testing and protection

Selective publications by GTLeader staff on ESD.

• Jaesik Lee, Ki-Wook Kim, Yoon Huh, Peter Bendix, and Sung-Mo Kang, “Chip-Level
  Charged-Device Modeling and Simulation in CMOS Integrated Circuits,” IEEE Transactions
  on Computer-Aided Design of Integrated Circuits and Systems, pp. 67 – pp. 81,
  vol. 22, Jan. 2003
• V. Axelrad, Yoon Huh, Jau-Wen Chen, and Peter Bendix, “A Novel CDM-like Discharge
  Effect during Human Body Model (HBM) ESD Stress,” IEICE Trans. Electronics, accepted
  for publication
• Leo G. Henry, “All ESD Standards Are Not Created Equal- An RS Analysis,”
  CE-Magazine, Jul/Aug, 2003
• Leo G. Henry, “All ESD Testing Types Are Not created Equal- Part I,”
  CE- Magazine, March/April, 2003
• Leo G. Henry, et al, “Real HBM and MM events- The dV/dT Threat,”
  EOS/ESD Symposium, 2003, pp. 179
• Leo G. Henry, et al, “Standardization of the TLP Methodology for ESD,”
  EOS/ESD Symposium, 2003, pp. 372
• Yoon Huh, V. Axelrad, Jau-Wen Chen, and Peter Bendix, “The Effects of Substrate
  Coupling on Triggering Uniformity and ESD Failure Threshold of Fully Silicided NMOS
  Transistors,” IEEE 2002 Symposium on VLSI Technology, pp. 220-221, 2002
• Jaesik Lee, Yoon Huh, Peter Bendix, and Sung-Mo Kang, “Noise-Aware Design for ESD
  Reliability in Mixed-Signal Integrated Circuits,” IEEE ASIC/SOC Conference,
  pp. 437-441, 2001
• Q. Li, Yoon Huh, Jau-Wen Chen, Peter Bendix, and Sung-Mo Kang, “Full Chip ESD Design
  Rule Checking,” IEEE International Symposium on Circuits and Systems (ISCAS),
  pp. V-503-506, 2001
• Jaesik Lee, Yoon Huh, Jau-Wen Chen, Peter Bendix, and Sung-Mo Kang, “Chip-Level
  Simulation for CDM Failures in Multi-Power ICs,” IEEE EOS/ESD Symp.,
  pp. 456-464, 2000
• Leo G. Henry et al, “TLP Calibration, Correlation, Standards, and New Techniques,”
  ESO/ESD Symposium, 2000, pp. 85
• Leo G. Henry et al, “Developing a Transient Induced Latch-up (TLU)-Standard for Testing
  Integrated Circuits,” EOS/ESD Symposium, 1999, pp.178

 

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