Testing

What Can GTLeader Provide for ESD Testing

Long testing time due to ever increasing chip size, and repeated zapping to the
same pin cause serious testing artifacts.

Current JEDEC spec and testing methodologies were developed some time ago.
ESD testing labs interpret the JEDEC spec in their own way.

• ESD/LU testing without “side effects”
- GTLeader provides optimized pin reduction method based on I/O ESD protection and
  power rail protection scheme analysis
- Split test method to avoid charging/cumulative stress effects

• Resident expertise on all required testing standards
- ESDA standards: HBM, MM and CDM Test methods
- ESDA standards: TLP (5.5.1-2003) Testing Method
- ESDA standards: Transient Latch-up-TLU-5.4.1 Methods
- IEC 6000-4-2 System Level (Human-metal) standard
- ESDA System Level std: Calibration Methodology
- AEC- automotive standards for HBM, MM and CDM
- EIA/JEDEC – JESD standards for HBM, MM and CDM
- AEC & EIA/JEDEC std for Latch-up (Static & Vectored)

• Guaranteed ESD testing
- GTLeader will backup test results for you when your customer raises any question on
  testing that GTLeader has provided